Low phase noise voltage controlled oscillator

ABSTRACT

Embodiments of the present invention include a low phase noise oscillator circuit using a current-reuse technique to reduce power consumption and improve phase noise, where the oscillator circuit comprises a first VCO coupled to a second VCO, and the outputs of the first and second VCOs are coupled with passive elements, such as capacitors. The overall power consumption of both the first and second VCOs is about the same as a single VCO. Furthermore, the phase noise is lowered by around 3 dB. Thus, the phase noise performance is improved without increasing the power consumption of the oscillator circuit.

BACKGROUND

1. Field

One or more embodiments of the present invention relate to the field ofelectronic circuits and systems and more particularly to voltagecontrolled oscillator circuits.

2. Discussion of Related Art

A voltage controlled oscillator (VCO) is a circuit that receives acontrol voltage and generates an output signal with a frequency that isa function of the control voltage. Fluctuations in the output signal ofthe VCO results in phase noise that is undesirable for the system.

In high linearity radio receivers, reciprocal mixing affects thesignal-to-noise ratio (SNR) and degrades the sensitivity of thereceiver. Reciprocal mixing may occur when the phase noise over 50 MHzaway mixes with blockers, which are undesired large signals fromexternal sources. These blockers degrade the SNR and as a result limitthe sensitivity of the receiver.

Typically, far-out phase noise in a VCO can be reduced by doubling theDC power/current while lowering the load resistance. As a result, theSNR improves by 3 dB for each doubling of power under ideal conditions.However, this increases the power dissipation of the VCO.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram that illustrates a voltage controlledoscillator circuit in accordance with one embodiment of the presentinvention.

FIG. 2 is a schematic diagram that illustrates a voltage controlledoscillator circuit in accordance with another embodiment of the presentinvention.

FIG. 3 is a schematic diagram that illustrates a voltage controlledoscillator circuit in accordance with yet another embodiment of thepresent invention.

FIG. 4 is a block diagram that illustrates a voltage controlledoscillator circuit coupled to a regulating module in accordance with oneembodiment of the present invention.

FIG. 5 is a block diagram that illustrates a front-end portion of radiodevice in accordance with one embodiment of the present invention.

FIG. 6 is a top plan view of arrangement of the inductors in accordancewith one embodiment of the present invention.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth inorder to provide a thorough understanding of one or more embodiments ofthe present invention. In other instances, well known electronic devicefunctionality and features have not been described in particular detailin order not to unnecessarily obscure this detailed description.

Embodiments of the present invention describe a voltage controlledoscillator (VCO) circuit that utilizes a current re-use technique toreduce power consumption and phase noise. The VCO circuit comprises afirst VCO coupled to a second VCO. The outputs of the first and secondVCOs are coupled with passive elements, such as capacitors. By couplingthe first VCO to the second VCO in series, the second VCO receivessubstantially the same amount of the supply current flowing through thefirst VCO. As a result, the overall power consumption of both the firstand second VCOs is about the same as a single VCO. Furthermore, thephase noise is lowered by around 3 dB. Thus, the phase noise performanceis improved without increasing the power consumption of the VCO circuit.

FIG. 1 is a schematic diagram of a voltage controlled oscillator (VCO)circuit 100. In an embodiment of the present invention, the VCO circuit100 comprises a first VCO 110 coupled to a second VCO 120 in series forcurrent re-use to reduce power consumption. In addition, the phase noiseis also reduced.

In an embodiment of the present invention, the first VCO 110 comprises afirst transistor M1 coupled to a second transistor M2. In oneembodiment, the first and second transistors M1, M2 are PMOStransistors. The source terminals of the first and second transistorsM1, M2 are coupled to a voltage supply terminal 180 to receive a lowsupply voltage Vdd. In one embodiment, the low supply voltage Vdd has arange of 1.0-1.5V, preferably around 1.2V. In one embodiment, a firstinductor L1 couples the source terminal of the first transistor M1 tothe voltage supply terminal 180. Similarly, a second inductor L2 couplesthe source terminal of the second transistor M2 to the voltage supplyterminal 180.

In one embodiment, a first capacitor C1 couples the source terminal ofthe first transistor M1 to a tuning voltage node 170 for biasing thefirst VCO 110. A second capacitor C2 couples the source terminal of thesecond transistor M2 to the tuning voltage node 170. In one embodiment,the first and second capacitors C1, C2 comprises capacitors havingvariable capacitance, which are also known as varactors.

The drain terminal of the first transistor M1 is coupled to the gateterminal of the second transistor M2. In one embodiment, a thirdcapacitor C3 couples the drain terminal of the first transistor M1 tothe gate terminal of the second transistor M2. The gate terminal of thefirst transistor M1 is coupled to the drain terminal of the secondtransistor M2. In one embodiment, a fourth capacitor C4 couples the gateterminal of the first transistor M1 to the drain terminal of the secondtransistor M2.

In one embodiment, a fifth capacitor C5 couples the drain terminal ofthe first transistor M1 to its source terminal. Similarly, a sixthcapacitor C6 couples the drain terminal of the second transistor M2 toits source terminal.

In one embodiment, the drain terminals of the first and secondtransistors M1, M2 are coupled to each other at a common drain node 161.In one embodiment, a third inductor L3 couples the drain terminal of thefirst transistor M1 to the common drain node 161. A fourth inductor L4couples the drain terminal of the second transistor M2 to the commondrain node 161. In an embodiment of the present invention, a seventhcapacitor C7 couples the common drain node 161 to a ground terminal. Inone embodiment, the seventh capacitor is a bypass capacitor.

In an embodiment of the present invention, the gate terminals of thefirst and second transistors M1, M2 are coupled to a bias node 190 forreceiving a bias voltage. In one embodiment, a first resistor R1 couplesthe gate terminal of the first transistor M1 to the bias node 190. Asecond resistor R2 couples the gate terminal of the second transistor M2to the bias node 190.

The first VCO 110 further comprises a differential output having a firstoutput 111 and a second output 112. In one embodiment, the drainterminals of the first and second transistors function as the firstoutput 111 and the second output 112.

The second VCO 120 has similar configuration as the first VCO 110, andthus will not be discussed in detail. Briefly, the second VCO 120 alsocomprises a first transistor M1 coupled to a second transistor M2. Thesource terminals of the first and second transistors M1, M2 of thesecond VCO 120 are coupled to each other. In one embodiment, the sourceterminals of the first and second transistors M1, M2 of the second VCO120 are coupled to common drain node 161 of the first VCO 110. The gateterminal of the first transistor M1 is coupled to the drain terminal ofthe second transistor M2. Similarly, the gate terminal of the secondtransistor M2 is coupled to the drain terminal of the first transistorM1.

The second VCO 120 comprises a differential output having a first output121 and a second output 122. In one embodiment, the drain terminals ofthe first and second transistors M1, M2 of the second VCO 120 functionas the first output 121 and the second output 122 of the second VCO 120.

The VCO circuit 100 further comprises a first passive element 610coupling the first output 111 of the first VCO 110 to the first output121 of the second VCO 120. In a specific embodiment, the first passiveelement 610 comprises a capacitor coupling the drain terminal of thefirst transistor M1 of the first VCO 110 to the drain terminal of thefirst transistor M1 of the second VCO 120.

A second passive element 620 couples the second output 112 of the firstVCO 110 to the second output 122 of the second VCO 120. In a specificembodiment, the second passive element 620 comprises a capacitorcoupling the drain terminal of the second transistor M2 of the first VCO110 to the drain terminal of the second transistor M2 of the second VCO120. The capacitor values of the first and second passive elements 610,620 are selected from a range that is sufficient to reduce phase noisewithout increasing the parasitic capacitance. In one embodiment, thecapacitor values of the first and second passive elements 611, 612 isless than 1 pF when the VCO circuit 100 has a operating frequency ofabout 10-12 GHz. In a specific embodiment, the capacitor values of thefirst and second passive elements 611, 612 is about 200-600 fF.

In an embodiment of the present invention, the first and second outputs111, 112 of the first VCO 110 function as the differential output of theoverall VCO circuit 100. Alternatively, the first and second outputs121, 122 of the second VCO 120 function as the differential output ofthe VCO circuit 100.

One advantage of the VCO circuit 100 is achieving low power consumptionwhile improving the signal-to-noise ratio (SNR). In the VCO circuit 100,the first VCO 110 and the second VCO 120 share the supply current Iddfrom the low supply voltage Vdd at the voltage supply terminal 180. Inother words, the second VCO 120 receives substantially the same amountof the supply current Idd flowing through the first VCO 110. As aresult, the overall power consumption of both the first and second VCO110, 120 is about the same as a single VCO. Furthermore, by coupling thefirst VCO 110 to the second VCO 120, the phase noise is reduced byaround 3 dB. Hence, the SNR improves by 3 dB without increasing thepower consumption of the VCO circuit 100. The first and second VCO 110,120 are each designed to operate at around 0.5-0.6V with very low phasenoise. In contrast, the conventional VCO requires a larger voltageand/or employs a linear regulator to reduce the supply voltage.

The VCO circuit 100 uses multiple inductors L1, L2, L3, L4, whichrequire large die area. In one embodiment, the less critical inductorsare arranged within the main frequency setting inductors so as to reusethe same die area. FIG. 6 illustrates a top plan view of the inductorsL1, L2, L3, L4 that are formed on a substrate 510. In an embodiment ofthe present invention, the inductors L3, L4 are formed around theinductors L1, L2.

It can be appreciated that the first and second transistors M1, M2 inthe first VCO 110 or second VCO 120 are not limited to using PMOStransistors. In other embodiments, the first and second transistors M1,M2 uses other types of transistors such as but not limited to NMOStransistors, bipolar junction transistors, or their combinations.

It can be appreciated that the VCO circuit 100 is not limited to onlytwo oscillators (i.e. the first and second VCOs 110, 120). Additionaloscillators can be added into the VCO circuit 100 to further improve thephase noise. For example, an additional oscillator can be coupled to thesecond VCO 120 in series. The outputs of the additional oscillator andthe second VCO 120 can be coupled in the same manner as the first andsecond VCOs 110, 120 shown in FIG. 1. Accordingly, the supply voltageVdd can be increased so that it is sufficient to operate the additionaloscillator.

In another embodiment of the present invention, an additional VCOcircuit is coupled to the VCO circuit 100 of FIG. 1 to further reducethe phase noise. FIG. 2 is a schematic diagram illustrating the VCOcircuit 100 coupled to another VCO circuit 101, the VCO circuit 101having a similar configuration as the VCO circuit 100.

The first and second outputs 111, 112 of the first VCO 110 are similarlycoupled to the first and second outputs 121, 122 of the second VCO 120.In an embodiment of the present invention, the first output 111 of thefirst VCO 110 is coupled to the first passive element 610. A thirdpassive element 630 couples the first output 121 of the second VCO 120to the first passive element 610. The second output 112 of the first VCO110 is coupled to the second passive element 620. A fourth passiveelement 640 couples the second output 122 of the second VCO 120 to thesecond passive element 620.

In one embodiment, the first, second, third and fourth passive elements610, 620, 630, 640 each comprises a capacitor having a range ofcapacitance that is sufficient to reduce phase noise without increasingthe parasitic capacitance. In a specific embodiment, the capacitor valueof the first, second, third and fourth passive elements 610, 620, 630,640 is less than 1 pF when the VCO circuit 100 has a operating frequencyof about 10-12 GHz.

The additional VCO circuit 101 comprises a third VCO 130 coupled to afourth VCO 140 in series. The third VCO 130 and the fourth VCO 140 havesimilar configurations as the first VCO 110 and second VCO 120, and thuswill not be discussed in detail herein. In an embodiment of the presentinvention, the third VCO 130 comprises a first output 131 and a secondoutput 132. In one embodiment, the drain terminals of the first andsecond transistors M1, M2 of the third VCO 130 function as the first andsecond outputs 131, 132.

The first output 131 of the third VCO 130 is coupled to the firstoutputs 111, 121 of the first and second VCOs 110, 120. In oneembodiment, a fifth passive element 650 couples the first output 131 ofthe third VCO 130 to the first and third passive elements 610, 630.Similarly, a sixth passive element 660 couples the second output 132 ofthe third VCO 130 to the second and fourth passive elements 620, 640.

The fourth VCO 140 comprises a first output 141 and a second output 142.In one embodiment, the drain terminals of the first and secondtransistors M1, M2 of the fourth VCO 140 function as the first andsecond outputs 141, 142.

The first output 141 of the fourth VCO 140 is coupled to the firstoutputs 111, 121, 131 of the first, second and third VCOs 110, 120, 130.In one embodiment, a seventh passive element 670 couples the firstoutput 141 of the fourth VCO 140 to the first, third, and fifth passiveelements 610, 630, 650. Similarly, an eighth passive element 680 couplesthe second output 142 of the fourth VCO 140 to the second, fourth andsixth passive elements 620, 640, 660. Hence, the outputs of the VCOcircuits 100, 101 are coupled in parallel. In other words, the firstoutputs 111, 121, 131, 141 of the first, second, third and fourth VCOs110, 120, 130, 140 are coupled to each other while the second outputs112, 122, 132, 142 are coupled to each other.

In an embodiment of the present invention, the fifth, sixth, seventh andeighth passive elements 650, 660, 670, 680 each comprises a capacitorhaving a range of capacitance that is sufficient to reduce phase noisewithout increasing the parasitic capacitance. In a specific embodiment,the capacitor value of the fifth, sixth, seventh and eighth passiveelements 650, 660, 670, 680 is less than 1 pF when the VCO circuit 101has a operating frequency of about 10-12 GHz.

An advantage of coupling the two VCO circuits 100, 101 is theimprovement in the SNR. By coupling an additional VCO circuit 101 to theVCO circuit 100, the SNR is further reduced by around 3 dB.

In an embodiment of the present invention, the outputs of the first VCO110 and third VCO 130 are DC coupled together instead of capacitivelycoupled because the first VCO and third VCO are operating atsubstantially the same DC potential. In other words, the outputs 111,112 of the first VCO 110 are directly coupled to the outputs 131, 132 ofthe third VCO 130 without passive elements 610, 620, 650, 660 asillustrated in FIG. 3. In this case, the third passive element 630couples the first output 121 of the second VCO 120 directly to the firstoutput 111 of the first VCO 110. The fourth passive element 640 couplesthe second output 122 of the second VCO 120 directly to the secondoutput 112 of the first VCO 110. Similarly, the seventh passive element670 couples the first output 141 of the fourth VCO directly to the firstoutput of the 131 of the third VCO 130. The eighth passive element 680couples the second output 142 of the fourth VCO 140 directly to thesecond output 132 of the third VCO 130.

Alternatively, the outputs of the second VCO 120 and the fourth VCO 140are directly coupled together without using passive elements because thesecond VCO 120 and the fourth VCO 140 are operating at substantially thesame DC potential (not shown). In this case, the output 121 is directlycoupled to the output 141 without the passive elements 630, 670, and theoutput 122 is directly coupled to the output 142 without the passiveelements 640, 680.

In an embodiment of the present invention, the output voltage of the VCOcircuit 100 is regulated to improve or stabilize the phase noiseperformance. During operation, temperature fluctuations or changes inthe transistors characteristics may affect the output voltage amplitudeof the VCO circuit 100, which causes inconsistent phase noiseperformance. In one embodiment, a constant output voltage amplitude isachieved by varying the supply voltage Vdd received by the VCO circuit100.

FIG. 4 is a block diagram that illustrates the VCO circuit 100 coupledto a regulating module 300 for regulating the differential output of theVCO circuit 100 so as to achieve constant output voltage amplitude. Inan embodiment of the present invention, the regulating module 300comprises a peak detector 310 coupled to the VCO circuit 100. In oneembodiment, the differential outputs 111, 121 of the VCO circuit 100 arecoupled to the peak detector 310. The peak detector 310 detects orsenses the output voltage amplitude of the VCO circuit 100 and sends acorresponding peak voltage to a comparator 330. In one embodiment, thecomparator 330 comprises an operational amplifier. The comparator 330compares the peak voltage of the peak detector 310 to a referencevoltage 320 and sends a control signal to a low dropout regulator (LDO)340 to regulate the output voltage of the LDO 340.

Typically, the LDO 340 operates from a raw 1.5V voltage supply from ahigh-efficiency switching regulator in the system. Depending on thecontrol signal from the comparator 330, the LDO 340 varies or adjustsits output voltage transmitted to the VCO circuit 100. In the case wherethe VCO circuit 100 operates on a supply voltage Vdd of around 1.2V, theoutput voltage of the LDO 340 to the VCO circuit 100 varies from about1.1V to 1.3V. Hence, the supply voltage Vdd is increased or decreasedover the range of 1.1V to 1.3V to maintain a relatively constant outputvoltage amplitude of the VCO circuit 100, which results in substantiallyconstant phase noise performance.

The regulating module 300 shown in FIG. 4 regulates the output voltageof the VCO circuit 100 in a continuous-time manner by utilizing the peakdetector 310 to continuously detect the output voltage amplitude. In analternative embodiment, the regulating module 300 comprises a statemachine and a digital-to-analog convertor (DAC) that sequences discretechanges in the output voltage to the VCO circuit 100. This results inless noise in the VCO circuit 100 and/or acceptable noise levels atlower power.

During operation of a radio device, reciprocal mixing may occur due tothe mixing of the phase noise with blockers. In this case, the blockerrefers to interferers from adjacent channel or out of channel signalsfrom other radio sources. Consequently, the reciprocal mixing affectsthe signal-to-noise ratio (SNR) and degrades the sensitivity of theradio device. In an embodiment of the present invention, a blockersensing means is used to activate the VCO circuit 100 when a blocker isdetected. In an embodiment of the present invention, the blocker sensingmeans is used to detect blockers that are present in high frequencies,for example 50 MHz or more away from the wanted signal.

FIG. 5 illustrates the front end portion of a radio device in accordancewith one embodiment of the present invention. In one embodiment, theradio device comprises an antenna 410 coupled to a low noise amplifier(LNA) 420. A blocker power sensor 430 is coupled to the LNA 420 todetect the presence of blockers or interfering signals from the outputof the LNA 420. In one embodiment, the blocker power sensor 430comprises a peak detector or a spectrum analyzer well known in the artfor detecting the blockers.

The blocker power sensor 430 is coupled to a frequency synthesizermodule 440 that includes the VCO circuit 100 and a low power oscillator200 that is operating at a lower power than the VCO circuit 100. Duringoperation, the blocker power sensor 430 activates the lower poweroscillator 200 when blockers are not detected. On the other hand, theblocker power sensor 430 activates the VCO circuit 100 when it detectsblockers, of insufficient amplitude that could lead to reciprocalmixing. In other words, the VCO circuit 100 is deactivated in theabsence of blockers so as to reduce the power consumption of the radiodevice.

The radio device further comprises a low noise multiplexer (MUX) 450coupled to the blocker power sensor 430, the VCO circuit 100 and the lowpower oscillator 200. A mixer 460 is coupled to the low noise MUX 450and LNA 420.

Typical radio receivers use pre-select filters for attenuating undesiredsignals at high frequencies. These pre-select filters take up space, areexpensive and have an insertion loss of around 2 dB, which degrades thesensitivity of the radio receiver. One advantage of implementing the VCOcircuit 100 in the radio device is the lowering of phase noise, whicheliminates the use of pre-select filters in a high-linearity radiodevice.

In an embodiment of the present invention, the VCO circuit 100 and theblocker power sensor 430 can be used for a low jitter clock for acontinuous time (CT) sigma delta analog-to-digital converter (ADC). CTsigma delta ADCs are generally sensitive to clock jitter. CT sigma deltaADCs have the advantages of achieving high dynamic range at low powerand smaller die area compared to discrete time sigma delta ADCs.

Several embodiments of the invention have thus been described. However,those ordinarily skilled in the art will recognize that the invention isnot limited to the embodiments described, but can be practiced withmodification and alteration within the spirit and scope of the appendedclaims that follow.

1. An oscillator circuit comprising: a first voltage controlled oscillator (VCO) to receive a supply voltage, the first VCO comprising a first output and a second output; a second VCO coupled to the first VCO to receive the supply current of the supply voltage, the second VCO comprising a first output and a second output; a first passive element coupling the first output of the first VCO to the first output of the second VCO; a second passive element coupling the second output of the first VCO to the second output of the second VCO; and a differential output comprising either the first and second outputs of the first VCO or the first and second outputs of the second VCO.
 2. The oscillator circuit of claim 1, wherein the first VCO further comprises a first transistor and a second transistor, the source terminals of the first and second transistors are coupled to a voltage supply terminal, the voltage supply terminal to receive the supply voltage, the gate terminal of the first transistor is coupled to the drain terminal of the second transistor, the gate terminal of second transistor is coupled to the drain terminal of the first transistor, and the drain terminals of the first transistor and the second transistor are coupled to a common drain node.
 3. The oscillator circuit of claim 2, wherein the second VCO further comprises a first transistor and a second transistor, the source terminals of the first and second transistors of the second VCO are coupled to the common drain node of the first VCO, the gate terminal of the first transistor of the second VCO is coupled to the drain terminal of the second transistor of the second VCO, and the gate terminal of second transistor of the second VCO is coupled to the drain terminal of the first transistor of the second VCO.
 4. The oscillator circuit of claim 3, wherein the first passive element comprises a capacitor coupling the drain terminal of the first transistor of the first VCO to the drain terminal of the first transistor of the second VCO; and wherein the second passive element comprises a capacitor coupling the drain terminal of the second transistor of the first VCO to the drain terminal of the second transistor of the second VCO.
 5. The oscillator circuit of claim 2, wherein the first VCO further comprises: a first inductor coupling the source terminal of the first transistor to the voltage supply terminal; a second inductor coupling the source terminal of the second transistor to the voltage supply terminal; a third inductor coupling drain terminal of the first transistor to the common drain node; and a fourth inductor coupling the drain terminal of the second transistor to the common drain node.
 6. The oscillator circuit of claim 5, wherein the first, second, third and fourth inductors of the first VCO are formed on a substrate, and wherein the third and fourth inductors are formed around the first and second inductors.
 7. The oscillator circuit of claim 5, wherein the second VCO further comprises: a first inductor coupling the source terminal of the first transistor to the common drain node of the first VCO; a second inductor coupling the source terminal of the second transistor to the common drain node of the first VCO; a third inductor coupling drain terminal of the first transistor to a ground terminal; and a fourth inductor coupling the drain terminal of the second transistor to the ground terminal.
 8. The oscillator circuit of claim 7, wherein the first, second, third and fourth inductors of the second VCO are formed on a substrate, and wherein the third and fourth inductors are formed around the first and second inductors.
 9. The oscillator circuit of claim 1, further comprising: a third VCO to receive the supply voltage, the third VCO comprising a first output and a second output; a fourth VCO coupled to the third VCO to receive the supply current of the supply voltage, the fourth VCO comprising a first output and a second output.
 10. The oscillator circuit of claim 9, further comprising: a third passive element coupling the first output of the second VCO to the first passive element; and a fourth passive element coupling the second output of the second VCO to the second passive element.
 11. The oscillator circuit of claim 9, further comprising: a fifth passive element coupling the first output of the third VCO to the first output of the fourth VCO, the fifth passive element coupling the first output of the third VCO to the first passive element; and a sixth passive element coupling the second output of the third VCO to the second output of the fourth VCO, the sixth passive element coupling the second output of the third VCO to the second passive element.
 12. The oscillator circuit of claim 11, further comprising: a seventh passive element coupling the first output of the fourth VCO to the fifth passive element; and an eighth passive element coupling the second output of the fourth VCO to the sixth passive element.
 13. The oscillator circuit of claim 1, wherein the supply voltage is regulated to maintain constant output voltage amplitude at the differential output.
 14. A radio device comprising: an antenna; a low noise amplifier coupled to the antenna; a blocker power sensor coupled to the low noise amplifier, the blocker power sensor operable to detect an interfering signal; a frequency synthesizer module coupled to the blocker power sensor, the frequency synthesizer comprising a first oscillator and a second oscillator, second oscillator to operate at a lower power than the first oscillator, the first oscillator comprising: a first voltage controlled oscillator (VCO) comprising a first output and a second output; a second VCO comprising a first output and a second output; a first passive element coupling the first output of the first VCO to the first output of the second VCO; a second passive element coupling the second output of the VCO oscillator to the second output of the second VCO; and a differential output comprising either the first and second outputs of the first VCO or the first and second outputs of the second VCO; and wherein the block power sensor activates the first VCO if the interfering signal is detected.
 15. The radio device of claim 14, wherein the blocker power sensor activates the second VCO if the interfering signal is not detected.
 16. The radio device of claim 14 further comprising a multiplexer coupled to the blocker power sensor, the first oscillator, and the second oscillator.
 17. The radio device of claim 16 further comprising a mixer coupled to the multiplexer and the low noise amplifier.
 18. The radio device of claim 14 further comprising: a peak detector coupled to the differential output of the first VCO for detecting the output voltage amplitude of the differential output; an operational amplifier coupled to the peak detector for comparing the output voltage amplitude of the differential output to a reference voltage so as to transmit a control signal; and a regulator coupled to the operational amplifier and the first oscillator, wherein the regulator is operable to receive the control signal from the operational amplifier and adjust an output voltage that is transmitted to the first VCO.
 19. The radio device of claim 14, wherein the first VCO further comprises a first transistor and a second transistor, the source terminals of the first and second transistors are coupled to a voltage supply terminal, the voltage supply terminal to receive the supply voltage, the gate terminal of the first transistor is coupled to the drain terminal of the second transistor, and the gate terminal of the second transistor is coupled to the drain terminal of the first transistor the drain terminals of the first transistor and the second transistor are coupled to a common drain node.
 20. The radio device of claim 19, wherein the second VCO further comprises a first transistor and a second transistor, the source terminals of the first and second transistors of the second VCO are coupled to the common drain node of the first VCO, the gate terminal of the first transistor of the second VCO is coupled to the drain terminal of the second transistor of the second VCO, and the gate terminal of second transistor of the second VCO is coupled to the drain terminal of the first transistor of the second VCO.
 21. The radio device of claim 20, wherein the first passive element comprises a capacitor coupling the drain terminal of the first transistor of the first VCO to the drain terminal of the first transistor of the second VCO; and wherein the second passive element comprises a capacitor coupling the drain terminal of the second transistor of the first VCO to the drain terminal of the second transistor of the second VCO. 